I2C (Inter-Integrated Circuit) Bus
The I2C bus was developed in the early 1980’s by Philips Semiconductors. Its original purpose was to provide an easy way to connect a CPU to peripheral chips in a TV-set. Now it is widely used to provide communication link between Integrated
Circuits,using just two wires - one wire for data and the other wire for clock. (This means that I2C is a synchronous data transmission standard.
As shown in the figure below, the I2C bus physically consists of 2 active wires and a ground connection. The active wires,called SDA and SCL, are both bi-directional. SDA is the Serial Data line, and SCL is the Serial Clock line. The SCL and SDA pins of every I2C compatible chip is open drain or open collector type. Therefore, pull-up resistors must be
connected from each line (SDA and SCL) to the power supply. When the bus is IDLE, the bus lines are in the logic HIGH state. To put a signal on the bus, the chip drives its output transistor, thus pulling the bus to a LOW level. When one chip is driving the bus LOW, all the other chips in the bus are not allowed to use the bus.
Acknowledge
An acknowledge (ACK) is sent by a slave, if the address sent by the bus master matches its own
address. After sending the address the bus master releases the SDA line, making it go high. After
that, the bus master generates another clock pulse through the SCL line and the slave with the
correct address pulls the SDA low. When an ACK is received, the bus master knows that a device
with that address exists in the bus.
The figure below shows a complete address transmission by the bus master. The bus master first sends the START condition. After that it transmits the 7-bit address 1010011, followed by a 0 to indicate that it wishes to write somethingto the device with that address. After writing each bit value (0 or 1) to the SDA line the bus master sends a clock pulse through SCL. The value of SDA is supposed be read out at the rising edge of the clock pulse. After the 8th clock pulse the bus master releases SDA. However, SDA is kept low by the slave to generate the ACK.
The I2C bus was developed in the early 1980’s by Philips Semiconductors. Its original purpose was to provide an easy way to connect a CPU to peripheral chips in a TV-set. Now it is widely used to provide communication link between Integrated
Circuits,using just two wires - one wire for data and the other wire for clock. (This means that I2C is a synchronous data transmission standard.
As shown in the figure below, the I2C bus physically consists of 2 active wires and a ground connection. The active wires,called SDA and SCL, are both bi-directional. SDA is the Serial Data line, and SCL is the Serial Clock line. The SCL and SDA pins of every I2C compatible chip is open drain or open collector type. Therefore, pull-up resistors must be
connected from each line (SDA and SCL) to the power supply. When the bus is IDLE, the bus lines are in the logic HIGH state. To put a signal on the bus, the chip drives its output transistor, thus pulling the bus to a LOW level. When one chip is driving the bus LOW, all the other chips in the bus are not allowed to use the bus.
Every device connected to the bus has its own unique address. Each device can act as a receiver and/or transmitter,depending on the functionality. For example a memory chip can act as a transmitter and a receiver at different times.
However, a digital to analogue converter (DAC) will normally act only as a receiver.
The I2C bus is a multi-master bus. This means that more than one IC capable of initiating a data transfer can be connected to it. The I2C protocol specification states that the IC that initiates a data transfer on the bus is considered the Bus Master.Consequently, at that time, all the other ICs are regarded to be Bus Slaves.Usually a microcontroller acts as a bus masters. When the bus is idel, both SDA and SCL lines are high. To start communication, the bus master issues a START condition. This acts as an ’Attention’ signal to all of the connected devices. All ICs on the bus will listen to the bus for incoming data. Then the bus master sends the ADDRESS of the device it wants to access, along with an indication whether the access is a Read or Write operation. Having received the address, all devices will compare it with their own address. If it does not match, they simply wait until the bus is released by the STOP condition . If the address matches, however, the chip will produce a response called the ACKNOWLEDGE signal. Once the bus master receives the acknowledge, it can start transmitting or receiving DATA. When all is done, the bus master will issue the STOP condition. This is a signal that the bus has been released and that the connected ICs may expect another transmission to start any moment.
Start Condition
Prior to any transaction on the bus, a START condition needs to be issued on the bus.
The start condition acts as a signal to all connected IC’s that something is about to
be transmitted on the bus. As a result, all connected chips will listen to the bus. The
chip issuing the START condition first pulls the SDA (data) line low, and next pulls
the SCL (clock) line low, as shown in the figure.
Stop Condition
After a message has been completed, a STOP condition is sent. This is the signal for
all devices on the bus that the bus is available again (idle). In a STOP condition, the
bus master first releases the SCL and then the SDA line as shown.
An acknowledge (ACK) is sent by a slave, if the address sent by the bus master matches its own
address. After sending the address the bus master releases the SDA line, making it go high. After
that, the bus master generates another clock pulse through the SCL line and the slave with the
correct address pulls the SDA low. When an ACK is received, the bus master knows that a device
with that address exists in the bus.
The figure below shows a complete address transmission by the bus master. The bus master first sends the START condition. After that it transmits the 7-bit address 1010011, followed by a 0 to indicate that it wishes to write somethingto the device with that address. After writing each bit value (0 or 1) to the SDA line the bus master sends a clock pulse through SCL. The value of SDA is supposed be read out at the rising edge of the clock pulse. After the 8th clock pulse the bus master releases SDA. However, SDA is kept low by the slave to generate the ACK.
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